Memory compilers use a concept called bit interleaving or MUX factors to improve immunity to soft error rate (SER). Bit interleaving is also used to provide multiple aspect ratio options for a given configuration of memory. Bit interleaving includes physical organization of a memory; i.e. an 8 word by 4 bit memory can be physically organized as MUX1 or MUX2 or MUX4. Further, through bit interleaving the memory can provide similar access to all words of the memory access and simultaneously provide multiple floor-plan options. For example, in a MUX4, the bits of a word “a” are interleaved with bits of a word “b”, “c” and “d”. This method of memory build encourages re-use of common circuits between the different MUX options.
The circuits used in different MUX factors only differ in placement of the cells. Physical layouts created for memory periphery created for one MUX factor are typically re-used for other MUX factors. This saves time in creating multiple layouts for the same circuits. The memory periphery circuits are pitch matched to the bit cell dimensions to ensure best overall area usage of the memory, re-use of layout cells and reduction in engineering efforts. Hence, circuits like sense amplifier, write driver, pre-charge, input latches and other COLUMN I/O circuits are aligned to one dimension of the bit cell and grow only in the tangential dimension.
Due to requirement of pitch matching to the bit cell dimensions, when a MUX2 is converted to a MUX4, the sense-amplifier and other COLUMN I/O circuits continue to be common to the set of 2 or 4 set of bits in a given column (based on MUX factor of 2 or 4). But it creates an additional space next to them in higher MUX factor implementations. The empty space next to a sense amplifier and other COLUMN I/O circuits causes unpredictable context next to the COLUMN I/O circuits. Context effects impact propagation delay of functional transistors from 5-18% depending on the circuit and context combination. Therefore, the unpredictable context leads to unknown timing for each circuit.